1. Technical Field
The present invention is directed generally toward a method and apparatus for processing data, and in particular, the present invention provides a method and apparatus for transferring data between two clock domains. Still more particularly, the present invention provides a method and apparatus for ensuring data integrity when synchronizing a transfer of data between a slower clock domain and a faster clock domain.
2. Description of the Related Art
Designs of computer systems and computer system architectures today can include the combination of one or more different subsystems with each subsystem having a different bus architecture. Subsystems are combined to facilitate the implementation of larger systems and typically known and standard subsystems are the ones selected for combining. By using known and standard subsystems, design time, manufacturing costs, design complexity, system maintenance and trouble shooting can all be reduced advantageously.
One standard bus architecture is the Peripheral Component Interconnect (PCI) bus standard. Computer systems can communicate with coupled peripherals using different bus standards including the PCI bus standard, or alternatively, using the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) bus standards. Recently, the IEEE 1394 serial communication standard has become a popular bus standard adopted by manufacturers of computer systems and peripheral components for its high speed and interconnection flexibilities. Each of the above communication standards communicates information (e.g., in data packets) at particular clock rates depending on the clock speed selected for the bus architecture.
In transferring or sharing data between different subsystems, data may be required to be synchronized because interconnected subsystems may not necessarily communicate or operate at the same clock frequency. With different bus architecture standards available within computer systems and communications systems, a computer device using one bus standard or “clock domain” may be coupled to and communicate with another computer or device using a different bus standard having a different clock domain. Interface circuits are employed to synchronize data transfers between different clock domains.
One issue that must be addressed by these interface circuits is to ensure data integrity in the transfer of data from one clock domain to another clock domain. This problem is present in transferring data across an asynchronous interface in which one side of the interface has reached the limit of available bandwidth. Write and data valid signals generated by traditional synchronization techniques may not be able to guarantee valid data when one of the clock domains serviced by the interface is bandwidth limited. When a transfer occurs on every clock cycle, the bandwidth is limited on one side of the clock domain. The problem that arises is that this amount of time may be insufficient for holding the data in the registers and synchronizing the new data to the other clock domain. As a result, a portion of the data within the registers may not be valid while other portions of the data within the register are valid when the data is synchronized across the clock domains.
Thus, it would be advantageous to have an improved method and apparatus for ensuring data integrity in synchronizing between a slower clock domain and a faster clock domain when data is transferred between the clock domains on every clock cycle in the slower clock domain.